Regviz

Espressif Systems /ESP32-S3 /SPI0 /SRAM_CMD

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as SRAM_CMD

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/Espressif Systems/ESP32-S3/SPI0/SRAM_CMD#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0SCLK_MODE 0SWB_MODE0 (SDIN_DUAL)SDIN_DUAL 0 (SDOUT_DUAL)SDOUT_DUAL 0 (SADDR_DUAL)SADDR_DUAL 0 (SCMD_DUAL)SCMD_DUAL 0 (SDIN_QUAD)SDIN_QUAD 0 (SDOUT_QUAD)SDOUT_QUAD 0 (SADDR_QUAD)SADDR_QUAD 0 (SCMD_QUAD)SCMD_QUAD 0 (SDIN_OCT)SDIN_OCT 0 (SDOUT_OCT)SDOUT_OCT 0 (SADDR_OCT)SADDR_OCT 0 (SCMD_OCT)SCMD_OCT 0 (SDUMMY_OUT)SDUMMY_OUT

Description

SPI0 external RAM mode control register

Fields

SCLK_MODE

SPI_CLK mode bits when SPI0 accesses to Ext_RAM. 0: SPI_CLK is off when CS inactive 1: SPI_CLK is delayed one cycle after CS inactive 2: SPI_CLK is delayed two cycles after CS inactive 3: SPI_CLK is always on.
SWB_MODE

Mode bits when SPI0 accesses to Ext_RAM.
SDIN_DUAL

When SPI0 accesses to Ext_RAM, set this bit to enable 2-bm in DIN phase.
SDOUT_DUAL

When SPI0 accesses to Ext_RAM, set this bit to enable 2-bm in DOUT phase.
SADDR_DUAL

When SPI0 accesses to Ext_RAM, set this bit to enable 2-bm in ADDR phase.
SCMD_DUAL

When SPI0 accesses to Ext_RAM, set this bit to enable 2-bm in CMD phase.
SDIN_QUAD

When SPI0 accesses to Ext_RAM, set this bit to enable 4-bm in DIN phase.
SDOUT_QUAD

When SPI0 accesses to Ext_RAM, set this bit to enable 4-bm in DOUT phase.
SADDR_QUAD

When SPI0 accesses to Ext_RAM, set this bit to enable 4-bm in ADDR phase.
SCMD_QUAD

When SPI0 accesses to Ext_RAM, set this bit to enable 4-bm in CMD phase.
SDIN_OCT

When SPI0 accesses to Ext_RAM, set this bit to enable 8-bm in DIN phase.
SDOUT_OCT

When SPI0 accesses to Ext_RAM, set this bit to enable 8-bm in DOUT phase.
SADDR_OCT

When SPI0 accesses to Ext_RAM, set this bit to enable 8-bm in ADDR phase.
SCMD_OCT

When SPI0 accesses to Ext_RAM, set this bit to enable 8-bm in CMD phase.
SDUMMY_OUT

When SPI0 accesses to Ext_RAM, in the DUMMY phase the signal level of SPI bus is output by the SPI0 controller.

Links

()

Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

 ()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data